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[Other Embeded program] seqdet

Description: 对串行输入的数据流进行检测的ＶＥＲＩＬＯＧ源代码-On the serial input data streams to detect the Verilog source code
Platform: | Size: 18432 | Author: 刘建明 | Hits:

[VHDL-FPGA-Verilog] keyboard

Description: verilog实现键盘驱动功能，具备基本字母按键输入，大小写转换功能，通过串口与主机实现交互-verilog to achieve keyboard-driven features, basic letter keys input, case conversion functions, interact with the host computer through the serial port
Platform: | Size: 1024 | Author: 柳林 | Hits:

[VHDL-FPGA-Verilog] LTC1407A

Description: LTC1407A仿真 可以模拟其全部功能 具有单端输入 时钟 串行输出-LTC1407A simulation can simulate all the functions in its single-ended input clock serial output
Platform: | Size: 1024 | Author: liu | Hits:

[Communication] ser2par

Description: 16位串行输入,并行输出，运用verilog语言编写，已通过测试-16-bit serial input, parallel output, using verilog language, has been tested
Platform: | Size: 1024 | Author: 张蓓蕾 | Hits:

[VHDL-FPGA-Verilog] ser_fir

Description: 用verilog实现一个8阶的改进串行FIR低通滤波器，输入数据位宽为12比特,经符号扩展后变为13比特。-With verilog order to achieve an improvement of 8 serial FIR low-pass filter, the input data bit width of 12 bits by sign extension into a 13-bit after.
Platform: | Size: 1024 | Author: hgdlsl | Hits:

[VHDL-FPGA-Verilog] ad5399

Description: AD5399是一款串行输入、双通道、12位数模转换器，可采用二进制补码数字编码。。 用Verilog实现其配置与功能-AD5399 is a serial input, dual-channel, 12-bit DAC, digital code can be twos complement. . Configuration and use Verilog functions to achieve its
Platform: | Size: 1024 | Author: dengxiaosong | Hits:

[VHDL-FPGA-Verilog] multiple-duts-and-drivers

Description: implementing verilog code for parallel input and serial output.-implementing verilog code for parallel input and serial output.
Platform: | Size: 3072 | Author: B N V Pavan kumar | Hits:

[VHDL-FPGA-Verilog] PS2_01

Description: 进阶实验_08_PS2_01 接受标准键盘输入，通过串口打印到PC，verilog-Advanced experimental _08_PS2_01 acceptable standard keyboard input through serial port to print to PC, verilog
Platform: | Size: 670720 | Author: 林爻 | Hits:

[VHDL-FPGA-Verilog] 4_12_SISO

Description: data path is serial input and data serial output for verilog code
Platform: | Size: 1024 | Author: ytkao | Hits:

[VHDL-FPGA-Verilog] Perl_for_CRC

Description: Cyclic Redundancy Check (CRC) is an error-checking code that is widely used in data communication systems and other serial data transmission systems. CRC is based on polynomial manipulations using modulo arithmetic. Some of the common Cyclic Redundancy Check standards are CRC-8, CRC-12, CRC-16, CRC-32, and CRC-CCIT. This application note discusses the implementation of an IEEE 802.3 CRC in a Virtex™ device. The reference design provided with this application note provides Verilog point solutions for CRC-8, CRC-12, CRC-16, and CRC-32. The Perl script (crcgen.pl) used to generate this code is also included. The script generates Verilog source for CRC circuitry of any width (8, 12, 16, 32), any polynomial, and any data input width.-Cyclic Redundancy Check (CRC) is an error-checking code that is widely used in data communication systems and other serial data transmission systems. CRC is based on polynomial manipulations using modulo arithmetic. Some of the common Cyclic Redundancy Check standards are CRC-8, CRC-12, CRC-16, CRC-32, and CRC-CCIT. This application note discusses the implementation of an IEEE 802.3 CRC in a Virtex ™ device. The reference design provided with this application note provides Verilog point solutions for CRC-8 , CRC-12, CRC-16, and CRC-32. The Perl script (crcgen.pl) used to generate this code is also included. The script generates Verilog source for CRC circuitry of any width (8, 12, 16, 32 ), any polynomial, and any data input width.
Platform: | Size: 90112 | Author: 尤恺元 | Hits:

[VHDL-FPGA-Verilog] And-serial-converter

Description: 实现1024位并行输入，32位串行输出的verilog HDL程序 并带有其测试程序-Achieve 1024 parallel input, 32-bit serial output verilog HDL program and with the test procedures and serial converter
Platform: | Size: 3072 | Author: lyj | Hits:

[VHDL-FPGA-Verilog] uart

Description: 用Verilog HDL编写的串口输入输出程序，可实现数据的传输，在DE2-70上测试通过，有很大的参考价值。-Prepared by the serial input and output using Verilog HDL program can achieve data transmission test by DE2-70, there is a great reference value.
Platform: | Size: 22063104 | Author: 李桐 | Hits:

[VHDL-FPGA-Verilog] uart

Description: Verilog 编写全双工UART input clk, // 这个模块的主时钟 input rst, // 同步复位信号 input rx, // 串口接收端口 output tx, // 串口发射端口 input transmit, // 发送信号 input [7:0] tx_byte, // 发送的字节 output received, // 表明，已接受到一个字节 output [7:0] rx_byte, // 接收的字节 output is_receiving, // 低电平时接收端在空闲状态 output is_transmitting, // 低电平时发送端在空闲状态 output recv_error // 表明，接收过程中发生错误-Verilog to write full-duplex UART master clock input clk,// ​ ​ this module the input rst// synchronous reset signal input rx// serial receive port output tx,// ​ ​ the serial transmitter port input transmit// send a signal input [7 : 0] tx_byte,// ​ ​ bytes sent output received// show that has received a byte output [7:0] rx_byte// the received byte output is_receiving,// ​ ​ low level when the receiving end in idle state OUTPUT is_transmitting,// ​ ​ low transmission side in the idle state output recv_error// indicate that an error occurred during reception
Platform: | Size: 1024 | Author: | Hits:

[VHDL-FPGA-Verilog] SinPout

Description: FPGA设计中涉及到的速度与面积互换技巧，本工程的代码用Verilog编写，实现功能串行输入并行输出-It comes to speed and area interchangeable FPGA design skills, the project code written in Verilog function serial input parallel output
Platform: | Size: 237568 | Author: wicoboy | Hits:

[VHDL-FPGA-Verilog] Verilog-Accumulator

Description: the folder contains two files written by Verilog HDL. the first one is an implementation of an accumulator that takes serial data as an input, and its output will be an accumulated sum of each consecutive four input samples. the second file is a test bench for the first file to test its operation
Platform: | Size: 1024 | Author: sawsan | Hits:

[MTK] bch_enc

Description: bch编码模块，verilog程序，串行输入，串行输出-The BCH encoding module, Verilog program, serial input, serial output
Platform: | Size: 1024 | Author: zhangbin | Hits:

[VHDL-FPGA-Verilog] cc

Description: CC217编程序，verilog实现，串行输入串行输出-CC 217 program, to achieve Verilog, serial input serial output
Platform: | Size: 1024 | Author: zhangbin | Hits:

[VHDL-FPGA-Verilog] 8_1

Description: 一个具有置位、复位、左移和右移功能的八位移位寄存器/“01011010”序列检测器。移位寄存器电路端口为：异步清零输入端口rst，输入时钟clk，置数判断输入端口load，移位类型判断输入端口m，数据输入端口data[7:0]，输出端口q[7:0]。序列检测器电路端口为：异步清零输入端口rst，输入时钟clk，串行数据输入端口d，输出标志端口s。(A eight bit shift register / 01011010 sequence detector with set, reset, left shift, and right shift function. Shift register circuit port is: Asynchronous Clear input port rst, input clock CLK, set the number to determine the input port load, shift type to determine the input port m, data input port data[7:0], output port q[7:0]. The sequence detector circuit port is: Asynchronous Clear input port rst, input clock CLK, serial data input port D, output flag port s.)
Platform: | Size: 94208 | Author: 白学 | Hits:

[VHDL-FPGA-Verilog] crc8_8_serial

Description: 自己编写的高效8位输入串行CRC-8 ATM程序(an effective program for 8bit serial input CRC-8 ATM calculate.)
Platform: | Size: 50176 | Author: asmreg | Hits:

[VHDL-FPGA-Verilog] xujiance

Description: 设计一个序检测电路，功能是检测出串行输入数据Data中的4位二进制序列1101（自左至右输入），当检测到该序列时，输出Out为1；没有检测到该序列时，输出输出Out为0，要求： （1）用状态机方法设计； （2）用Verilog HDL语言设计，用Modelsim软件做功能仿真。(A sequence detection circuit is designed to detect the 4 bit binary sequence 1101 in the serial input data Data (from left to right). When the sequence is detected, the output Out is 1. When the sequence is not detected, the output Out is 0. (1) design by state machine method; (2) design with Verilog HDL language and use Modelsim software to do functional simulation.)
Platform: | Size: 1024 | Author: spysleeper | Hits:
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